This page lets you access a comprehensive collection of Cell Matrix-related articles, papers, book chapters, abstracts, white papers, patents, talks, seminars, courses, and any other publicly available written information about research and development work utilizing Cell Matrix technology. Full bibliographic references are also available.
 
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  Books, Papers, Articles, Conference Abstracts, Grant Abstracts
 
Self-Organizing Digital Systems
a book chapter by N. Macias and L. Durbeck, 2008.
[book at Springer or Barnes & Noble or Amazon]
summarizes all Cell Matrix research to date to provide the necessary basic building blocks of an engineered (nonstatistical) approach to self-organizing digital electronic systems, and the gamut of immediate future work needed in Cell Matrix research, including incorporating self-modification into a hardware specification tool
Application of Self-Configurability for Autonomous, Highly-Localized Self-Regulation
a paper by N. Macias and P. Athanas, 2007.
[Abstract] [ PDF at IEEE ] [request an offprint]
describes a Cell Matrix implementation of electronic stem cells that self replicate and differentiate
A hardware implementation of the Cell Matrix self-configurable architecture: The Cell Matrix MOD 88Ö
a paper and demonstration by N. Macias and L. Durbeck, 2005.
[Abstract]
[Online Demo] [PDF at IEEE ] [request an offprint]
At EH 2005, Nick Macias demo'ed a small 8x8 array of Cell Matrix cells in hardware that is available for anyone's use online for free here
Obtaining quadrillion-transistor logic systems despite imperfect manufacture, hardware failure, and incomplete system specification
a book chapter by L. Durbeck and N. Macias, 2004.
[Abstract] [a few pages] [book at Springer or Barnes & Noble or Amazon]
Logic designers could reap many of the benefits—and minimize many of the pitfalls—of nanoelectronics by using the approach sketched out in this chapter.
Nano, Quantum and Molecular Computing:
Implications to High Level Design and Validation

a book edited by S. K. Shukla and R. I. Bahar, 2004.
[
Table of Contents] [book at Springer or Barnes & Noble or Amazon]
This book is a collection of researchers' work to develop tools, architectures and plans for integrating new kinds of electronics fabrication methods—such as nanoelectronics, quantum dots, molecular switches, etc—into logic systems, circuits, and other products. Emphasis is given to the ways in which the use of nanoelectronics is expected to differ from the current use of silicon field-effect transistors and custom ASIC fabrication of products, and how this changes the tools and the logic systems designs themselves.
    There are many levels at which systems integration is expected to be different, and some of the research is focused on developing good models of individual or aggregate, statistical device behavior, and on developing good substructures for systems integration above the device level but below the target circuit or system design level.
Adaptive methods for growing electronic circuits on an imperfect synthetic matrix
a paper by N. Macias and L. Durbeck, 2004.
[Abstract] [published paper, requires a fee ] [final draft, PDF] [request an offprint]
a complete description of a self-repairing system
Evolvable Components: From Theory to Hardware Implementations
a book by L. Sekanina, 2003.
[Abstract] [more information]
research to make Evolvable Hardware more accessible to circuit designers for building dynamically adaptive circuits that can change based on changes in their "environment" (which could be changes in the operating conditions, or changes to the desired operation, or changes in the patterns of inputs received by the circuit, etc). Chapter 2 and the Future Work section have a bit about the Cell Matrix architecture. Dr. Sekanina says that it would be a natural platform for further applying his techniques.
Automated Placement and Routing of Cell Matrix Circuits
a Master's thesis by D. Yatsenko, 2003.
[Abstract] [thesis, PDF]
research exploring several iterative algorithms to create a Cell Matrix circuit layout without user intervention
Defect-tolerant, fine-grained parallel testing of a Cell Matrix
a paper by L. Durbeck and N. Macias, 2002.
[Abstract] [paper, PDF] [paper, gzip'd postscript]
summarizes a testing method for Cell Matrices, including a means to test one cell and a means to access each cell efficiently
Self-Assembling Circuits with Autonomous Fault Handling
a paper by N. Macias and L. Durbeck, 2002.
[Abstract] [paper, PDF] [gzip'd postscript]
a concise summary of techniques developed to permit Cell Matrix circuits to lay themselves out on hardware despite hardware defects or faults
Implementation of a dynamic programming algorithm for DNA sequence alignment on the Cell Matrix architecture
a Master's thesis by B. Wang, 2002.
[Abstract] [thesis, PDF]
research demonstrating that a high performance parallel machine can be constructed on a Cell Matrix for lining up DNA or other protein sequences
Towards Nanocomputer Architecture
a paper by P. Beckett and A. Jennings, 2002.
[Abstract] [paper, PDF]
a prediction of the features that nanoscale fabrication will require of a nanoscale hardware architecture, and a review of the literature for candidate architectures
A Process Driver for Nanofabrication: Detecting and Analysing Hardware Defects using the Cell Matrix Computing Architecture
a conference abstract by L. Durbeck and N. Macias, 2001.
[Abstract]
applicability of our research to some current challenges in molecular engineering
Fiber Computing: towards more wearable computing
a paper by O. Cakmakci, M. Koyuncu, M. Eber-Koyuncu, E. Duriau, A. Matthewson, J. Donnely, B. O'Neill, T. Healy, F. Clemens, 2001.
[Abstract] [paper, PDF]
reports on progress to date on project to embed silicon into fibers, and discusses applicability of Cell Matrix architecture to flexible computers woven of fibers
A Totally Distributed Genetic Algorithm:
From a Cellular System to the Mesh of Processors

a paper by L. Sekanina, Dvo°ßk, V., 2001.
[Abstract] [paper, PDF]
investigation of the parallel scalability of Macias' Ringed Genetic Algorithm (RGA)
Autonomously Self-Repairing Circuits
a Small Business Innovative Research grant Proposal Summary by L. Durbeck and N. Macias, 2000.
[Abstract]
describes a project done for NASA and its significance and potential commercialization
The Cell Matrix: An Architecture for Nanocomputing
a paper by L. Durbeck and N. Macias, 2000.
[Abstract] [paper, PDF] [web version of an earlier draft] [texte en franšais, PDF] [texte en franšais, html] [Poster] [DES Cracker Simulation]
describes the architecture's applicability to atomic-scale fabrication
The published version of this paper is provided here courtesy of the publisher of Nanotechnology, the Institute of Physics. The translation of this paper into French is courtesy of Aurélien Sagnier, French professional translator, who created this translation for his PhD thesis.
Review: First NASA DOD Workshop on Evolvable Hardware 1999
an article by Julian F. Miller, 2000.
[paper, PDF] [postscript] [gzip'd postscript] [web version]
The cell matrix architecture is included here in Miller's analysis of significant progress in evolvable hardware presented at the conference
Review of Proceedings of the First NASA/DoD Workshop on Evolvable Hardware
an article by Hugo de Garis, 1999.
[review, web version]
an enthusiastic review of the cell matrix by a prominent member of the reconfigurable hardware community
The PIG Paradigm: The Design and Use of a Massively Parallel Fine Grained Self-Reconfigurable Infinitely Scalable Architecture
a paper by Nicholas J. Macias, 1999.
[Abstract] [paper, PDF] [postscript] [gzip'd postscript]
a general overview of the cell matrix architecture with a partial list of potential applications
Ring Around the PIG: A Parallel GA with Only Local Interactions Coupled with a Self-Reconfigurable Hardware Platform to Implement an O(1) Evolutionary Cycle for EHW
a paper by Nicholas J. Macias, 1999.
[Abstract] [paper, PDF] [postscript] [gzip'd postscript]
an application of the cell matrix to a spatially-distributed population of evolving circuits
   
  Talks
 
"The Sound of One Hand Clapping," talk given by N. Macias on 11/19/2007 at Villanova University Department of Computing Sciences [Abstract]
Macias described how Cell Matrix research has tackled some fundamental questions in Computer Engineering
"Dealing with Chip Defects and Chip Failures, for Cell Matrix Chips," talk given by L. Durbeck on July 30, 2002 at SPIE ITCOM 2002, Reconfigurable Technology. [Abstract] [paper, PDF] [paper, gzip'd postscript]
Durbeck described a two-tiered design for fault testing each cell on a Cell Matrix chip
"Autonomous Self-Assembling Circuits with Automatic Fault Handling," talk given by N. Macias on July 17, 2002 at EH2002. [Abstract] [paper, PDF] [paper, gzip'd postscript]
Macias described a suite of techniques developed so that a Cell Matrix circuit could automatically regenerate itself without outside intervention
"A Simple, Powerful Build Target for Nanoelectronics," talk given by N. Macias on June 27, 2002 at Nanospace 2002. [Abstract]
Macias provided several compelling arguments why a Cell Matrix is easier to build than other kinds of hardware, and why it is preferable for extremely dense, high switch count hardware
"Underlying Future Technology talk on Computing: Scaling Up, Scaling Down, and Scaling Back," talk given by L. Durbeck on September 11, 2001 at The International Meeting on Mathematical Methods for Nuclear Applications. [Abstract]
a talk discussing the roles this technology may play in scientific computing
"An Approach to Designing Extremely Large, Extremely Parallel Systems," talk given by L. Durbeck on April 26, 2001 at The Conference on High Speed Computing. [Abstract]
Cell Matrix algorithms, hardware and architecture were applied in this talk to the task of constructing and using an Avogadro-scale computer
"Gate Array, Configure Thyself," talk given by N. Macias on April 26, 2001 at The Conference on High Speed Computing. [Abstract]
talk identifying key architectural features and their merits
"Benefits and Applications of Self-Configurable Hardware: The Cell Matrix Architecture," talk given by N. Macias, December 7, 2000 at Starlab, Brussels, Belgium. [Abstract]
a talk discussing the significance of self-reconfigurability
   
  Patents
 
US Patent #6,577,159, "Method and Apparatus for Automatic High-Speed Bypass Routing in a Cell Matrix Self-Configurable Hardware System" by Nicholas J. Macias and Murali Dandu Raju. [Abstract] [patent, PDF]
a technique for implementing hardware wires when software calls for them
US Patent #6,297,667, "Circuits and Sequences for Enabling Remote Access to and Control of Non-Adjacent Cells in a Locally Self-Reconfigurable Processing System Composed of Self-Dual Processing Cells," by Nicholas J. Macias. [Abstract] [patent, PDF]
software techniques for programming the truth tables of cells
US Patent #6,222,381, "Self-configurable parallel processing system made from self-dual code/data processing cells utilizing a non-shifting memory," by Lisa J.K. Durbeck and Nicholas J. Macias. [Abstract] [patent, PDF]
all details of a denser version of the architecture
US Patent #5,886,537, "Self-Reconfigurable Parallel Processor Made From Regularly-Connected Self-Dual Code/Data Processing Cells," by Nicholas J. Macias, Murali Dandu Raju and Lawrence B. Henry III.
[Abstract] [patent, PDF] [postscript] [gzip'd postscript]
disclosure of all details of the architecture and its operation